1. Field of the Invention
The present invention provides a method and related circuit for driving a chip to output signals, and more particularly, a method and related circuit that use a plurality of inverters with equivalent loads to form an even number inverter driving circuit to drive output signals.
2. Description of the Prior Art
In modern society, microprocessor chips that process information are one of the most important hardware components for various information products. There are usually numerous logic gates in chips to perform certain functions; however, in practical circuit operation, logic gates also introduce some imperfect factors such that a signal profile of the logic circuit is not as expected. So it is one of the major topics for the modern IT industry to construct circuit design that minimizes the effect of these imperfections.
Please refer to FIG. 1A. FIG. 1A is a circuit diagram for a prior art chip 10. In the chip 10, there are three driving circuits 14A, 14B, and 14C connected in between circuits 12 and 16. Signals output from an output end co of the circuit 12 to the driving circuit 14A. An output signal from an output end co of the circuit 12 is an input signal sp0 of the driving circuit 14A. There is one input end i1 and one output end o1 in the driving circuit 14A, one input end i2 and four output ends o2 in the driving circuit 14B, and four input ends i3 and 16 output ends o3 in the driving circuit 14C. The driving circuits 14A to 14C all use inverters M as a driving unit to drive signals. There is one inverter M in the driving circuit 14A, its input connects to the input end i1 of the driving circuit 14A, and the output end of the inverter M is connected to the output end o1 of the driving circuit 14B. In order to match all output ends o2 of the driving circuit 14B, there are also four inverters M in the driving circuit 14B, their output ends connect to various output ends o2 respectively, and the output ends of the inverters are connected to the input end i2. Similarly, in order to match the output ends o3 of the driving circuits a 14C, there are also 16 inverters M in the driving circuit 14C, their output ends connect to input end o3 respectively. In order to match the input end i3 of the driving circuit 14C, every four input ends of the inverters are connected to the same input circuit i3, as shown in FIG. 1A. In other words, the inverter in driving circuit 14A, inverts input signal sp0 and outputs driving signal spy, which is then fanned out to four inverters of the driving circuit 14B. The two inverters of the driving circuit 14B then invert and drive driving signal sp1 into driving signals sp2, and then fan out to the four inverter groups (four inverters in each group) of the driving circuit 14C. Finally, in order to match the eight input ends o3 of the driving circuit 14C, there are also 16 corresponding driving ends d3 in the output circuit 16. The driving signal sp3 that is driven by all inverters in the driving circuit 16 is output via each driving end d3 to the output circuit 16.
However, the allocation of a plurality of inverters M in chip 10, results in signal distortion that causes duty cycle distortion of signal sp3 because of inverter M mismatch. For instance, if the channel width ratio of a p-type MOSFET and an n-type MOSFET of an inverter M is 9 μm:1 μm, and the lengths are both 0.22 μm, a CMOS mismatch in inverter M results. Suppose every driving end d3 of the circuit 16 has a input load equivalent to four inverters M (as shown in FIG. 1A, i.e. every inverter M in driving circuit 14C has to push a load that is equivalent to four inverters), the duty cycle of the input signal sp0 is 50%, but the duty cycle of signal sp3 will be distorted to 51.85%. Please refer to FIG. 1B. If the driving circuit allocation between the circuits 12 and 16 changes to two levels 17A, 17B, and every driving end d3 of the circuit 16 has a load that is equivalent to 16 inverters, then the inverters of the driving circuit 17A only need to drive the load of 4 inverters in the driving circuit 17B. However, each inverter in the driving circuit 17B has to drive the load of 16 inverters. Under such a mismatched load, if a signal sp0 has a duty cycle of 50%, the duty cycle of the signal sp3 will be seriously distorted to 63.25%.
The reason that the prior art inverter allocation causes duty cycle distortion is discussed as follows. Please refer to FIG. 2. FIG. 2 is a typical circuit diagram of an inverter M. There is one p-type MOSFET Qp and one n-type MOSFET Qn in the inverter M, which function as a current source and a current sink respectively. Gate ends of the transistors Qp, Qn are electrically connected to an input end i0 of the inverter, and sources of the transistors Qp, Qn are electrically connected to a DC bias supply Vd and ground G respectively. Drains of the transistors Qp, Qn are electrically connected to a node Nop, which becomes the output end of inverter M. The circuit that the output end of inverter M connects to has an equivalent input impedance that is the equivalent load Zp0 of the inverter M. In a logic circuit, output ends of the inverter M are usually connected to another logic gate, so the equivalent load of the inverter M can be viewed as a capacitance. When the signal voltage level of the input end i0 of the inverter M is at a low level, the transistor Qn will conduct and provide charge current to charge the equivalent load Zp0 and raise the voltage level of the node Nop. Relatively, when the voltage level of the input end i0 of the inverter M is at a high level, the transistor Qp will conduct and absorb charge current from Nop to discharge the equivalent load Zp0, making the voltage level of the node Nop drop. Hence, the signal driving power of the inverter M depends on the amount of charge and discharge current that can be conducted by transistors Qp, Qn.
As described, because inverters provide the signal driving capability of the driving circuits 14A to 14C, the waveform of the driving signal depends on the inverter M. Please refer to FIG. 3A (and also FIG. 2). FIG. 3A is an ideal inverter input-output waveform timing chart, where a horizontal axis of FIG. 3A is time and a vertical axis is signal voltage level. A dotted waveform 17A is an input waveform at the input end i0, and a waveform 17B is an output waveform at the node Nop. In an ideal inverter, conductivity of transistors Qp and Qn is compatible and matched (that is, the amount of charge and discharge current is the same). So, the rise time for the output signal voltage waveform at the node Nop from a low level to a high level is the same as the fall time from the high level to the low level. As shown in FIG. 3A, at a point t0, the dotted waveform 17A at the input end i0 changes from a low level to a high level. The inverter M starts to discharge and node Nop voltage drops to the low level, and point t1 discharge finishes, as shown as waveform 17B. Similarly, at a point t2, the waveform 17A at the input end i0 changes from the low level to the high level, and the inverter M starts to charge the node Nop to raise its voltage until point t3. If the inverter M has ideal matching driving capability for charge and discharge, the duration between the points t0 to t1 is the same as t2 to t3. If the waveform of the input end i0 is a 50% duty cycle waveform (as shown in FIG. 3A), then the output driving waveform of the ideal inverter M will also have a 50% duty cycle. In other words, output voltage waveform 17B of node Nop will have consistent time periods from rising to falling and from falling to rising, that is, time period Tp0.
However, if the transistors Qn, Qp of the inverter M are not matched for charge and discharge, the waveform quality of the output waveform at the node Nop will be affected. Even with a 50% duty cycle of the input end i0 waveform, the output waveform from the node Nop cannot maintain a 50% duty cycle. Please refer to FIG. 3B regarding this imperfection (also refer to FIG. 2 and FIG. 3A). FIG. 3B is a timing chart of the input-output waveform of an imperfect inverter. A horizontal axis of FIG. 3B is time, and a vertical axis is signal voltage level. A dotted waveform 17A is the input waveform from the node Nop at the inverter input end (consistent with the waveform 17A of FIG. 3A), and a waveform 17C is the output waveform at the node Nop. A mismatched semiconductor process makes the capability of driving discharge current of the transistor Qn less than the capability of driving charge current of the transistor Qp. At a point t0, when the input waveform 17A increase from a low level to a high level, the inverter M needs more time (until a point t1b) to discharge the node Nop waveform from a high level to a low level. Relatively, when the input waveform 17A at point t2 drops from the high level to the low level, the transistor Qp with better driving capability can charge output waveform 17C from a low level to a high level in a short period (from point t2 to point t3). In this way, even with a 50% duty cycle input waveform, a period Tp1 from rising to falling of the node Nop output waveform will be greater then a period Tp2 from failing to rising, and the waveform 17C cannot maintain a 50% duty cycle. In other words, when the inverter M has mismatched transistors, the waveform of driving output for inverter M will be distorted, and cannot have the same duty cycle as the input waveform. This type of duty cycle distortion will lead to a timing error, waveform distortion in logic circuits, and even errors in circuit function.
Because of the limited precision of semiconductor processes, inverter mismatch is not impossible. Mismatch will cause waveform distortion and limit the margin of error allowed during circuit operation. In the prior art driving circuit design principles, circuit design to correct or compensate the negative effects of inverter mismatch is not taught.